The invention relates to chemical mechanical planarizing (CMP) formulations for removing barrier metals and, more particularly, to polishing compositions for selectively removing barrier metals in the presence of interconnect structures in integrated circuit devices.
In recent years, the semiconductor industry has increasingly relied upon copper electrical interconnects in forming integrated circuits. These copper interconnects have a low electrical resistivity and a high resistance to electromigration. Since copper is very soluble in many dielectric materials, such as silicon dioxide and low-K or doped versions of silicon dioxide, a diffusion barrier layer is necessary to prevent the diffusion of copper into the underlying dielectric material. Typical barrier materials include, tantalum, tantalum nitride, tantalum-silicon nitrides, titanium, titanium nitrides, titanium-silicon nitrides, titanium-titanium nitrides, titanium-tungsten, tungsten, tungsten nitrides and tungsten-silicon nitrides.
In response to increasing demands for high density integrated circuits, semiconductor producers now fabricate integrated circuits containing multiple overlying layers of metal interconnect structures. During device fabrication, planarizing each interconnect layer improves packing density, process uniformity, product quality and most importantly, enables manufacturing of multiple layer integrated circuits. Semiconductor producers rely upon chemical-mechanical-planarizing (CMP) as a cost effective means of producing flat substrate surfaces. The CMP process is typically carried out in a two-step sequence. First, the polishing process uses a “first-step” slurry specifically designed to rapidly remove copper.
After the initial copper removal, a “second-step” slurry removes the hard barrier material. Typically, second-step slurries require excellent selectivity to remove the barrier material without adversely impacting the physical structure or electrical properties of the interconnect structure. Because high-conductivity interconnect metals, such as copper are softer than typical barrier materials, such as tantalum nitride and titanium nitride, conventional bulk copper removal slurries are not useful for barrier applications. Acidic barrier slurries accomplish the selectivity by introducing sufficient benzotriazole into the slurry to decrease the copper removal rate.
Tunability of the copper and dielectric, such as TEOS, rates in the barrier polishing step is important. For purposes of this specification, TEOS represents the dielectric produced from tetraethylorthosilicates. For example, Liu et al. in US Pat. Pub. No. 2005/0031789, disclose an acidic barrier slurry with the use of a quanternary ammonium salt for increasing TEOS removal rates. This slurry provides the advantage of excellent barrier removal rate with low copper rate and with a controlled TEOS removal rate. Furthermore, the hydrogen peroxide level provides an effective toggle for controlling copper removal rate. Unfortunately, these slurries lack control for low-K dielectrics, such as carbon-doped oxides (CDO).
Because integration schemes used by different IC manufacturers vary; the rate selectivity required for the various films polished in the barrier CMP step also varies. Certain film stacks require higher copper, TEOS and CDO rates for topography correction; but on other occasions, low copper, TEOS and CDO are useful. A barrier removal slurry that can correct profiles for copper, TEOS and CDO will facilitate further decreases in line width.
In view of the above, there exists a need to provide a second-step slurry that possesses a high removal rate of barrier materials, excellent selectivity to interconnect metals, controlled removal of TEOS, CDO and copper removal rates.